Bölüm 9 · SimülatörPaging & Address Translation? ← Bölüm 9 Page 256 512 1K 2K 4K Pages 8 Frames 6 TLB 4 1.5/sVAs Demo Locality Random 1Issue VA 2Split p | d 3TLB 4Page table 5PhysicalVirtual–➜Physical– Page tablepage · present · framePhysical memory ClosePaging & Address TranslationThe CPU issues virtual addresses (VAs). Each VA is split into a page number p (high bits) and an offset d (low bits). The TLB is checked first; on a TLB miss the page table is read. A present page gives its frame f, and the physical address is f × page size + d. A page whose present bit is 0 causes a page fault.How to useSet the page size, the number of virtual pages, physical frames and TLB entries in the top row.Type the virtual addresses (decimal, separated by spaces) or pick a preset; the shuffle button randomizes the page table.Play, or step through the five stages of each translation.Edit the page table at any step: click a present bit or type a frame number.The chart button compares TLB hits for TLB sizes 1–8 on the same address list; click a bar to use that size.TermspPage number = VA div page size (high bits).dOffset = VA mod page size (low bits), copied unchanged.TLBCache of recent page → frame mappings; the least recently used (LRU) entry is replaced.Present1 = page is in a frame; 0 = page fault.PAframe × page size + d.EditFrames stay unique (a used frame swaps). The edited page's TLB entry is invalidated.Legend p bits d bits f bits / new TLB entry ✓ TLB hit ✗ miss / faultKeys←→ stepSpace playHomeEnd first / lastEsc close